1m x 4 static ram cy7c1046bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-11924 rev. ** revised november 30, 2006 features ? low active power ? 825 mw (max) ? low cmos standby power ? 44 mw (max) ? 2.0v data retention (400 w at 2.0v retention) ? automatic power down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features ? available in non pb-free 400 mil wide 32-pin soj package functional description the cy7c1046bn is a high performance cmos static ram organized as 1,048,576 words by 4 bits. easy memory expansion is provided by an active low chip enable (ce ), an active low output enable (oe ), and tri-state drivers. you write to the device by taking chip enable (ce ) and write enable (we ) inputs low. data on the four io pins (io 0 through io 3 ) is then written into the location specified on the address pins (a 0 through a 19 ). you read from the device by taking chip enable (ce ) and output enable (oe ) low while forcing write enable (we ) high. under these conditions , the contents of the memory location specified by the address pins appears on the io pins. the four input and output pins (io 0 through io 3 ) are placed in a high impedance state when t he device is deselected (ce high), the outputs are disabled (oe high), or when the write operation is active (ce low, and we low). the cy7c1046bn is available in a standard 400-mil-wide 32-pin soj package with center power and ground (revolu- tionary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer power down we oe io 0 io 1 1m x 4 array io 3 io 2 a 0 a 11 a 13 a 12 a ce a a 16 a 17 1 2 3 4 5 6 7 8 9 10 12 21 22 25 24 23 28 27 26 top view soj 11 29 32 31 30 14 13 19 20 gnd a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 we v cc a 18 a 15 a 12 a 14 io 2 1046b?1 a 9 a 0 io 0 io 1 oe a 17 a 16 a 13 ce 1046b?2 a 9 a 18 16 15 17 18 gnd io 3 v cc a 10 a 11 a 19 nc a 10 a 19 selection guide 7c1046bn-15 maximum access time (ns) 15 maximum operating current (ma) 150 maximum cmos standby current (ma) 8 [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 2 of 9 maximum ratings exceeding maximum ratings may impair the useful life of the device. user guidelines are not tested. storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc relative to gnd [1] .... ?0.5v to +7.0v dc voltage applied to outputs in high-z state [1] ....................................?0.5v to v cc + 0.5v dc input voltage [1] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... .............. .............. ....... >2001v (in accordance with mil-std-883, method 3015) latch-up current ..................................................... >200 ma operating range range ambient temperature [2] v cc commercial 0 c to +70 c 4.5v?5.5v electrical characteristics over the operating range parameter description test conditions 7c1046bn-15 min max unit v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 v v ol output low voltage v cc = min, i ol = 8.0 ma 0.4 v v ih input high voltage 2.2 v cc + 0.3 v v il input low voltage [1] ?0.3 0.8 v i ix input load current gnd < v i < v cc ?1 +1 ma i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ma i cc v cc operating supply current v cc = max, f = f max = 1/t rc 150 ma i sb1 automatic ce power down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max 20 ma i sb2 automatic ce power down current ? cmos inputs max v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 8ma capacitance [3] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 6pf c out io capacitance 6 pf notes 1. v il (min) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the ?instant on? case temperature. 3. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 3 of 9 ac test loads and waveforms switching characteristics (over the operating range) [4] 7c1046bn-15 parameter description min max unit read cycle t power v cc (typ) to the first access [5] 1 s t rc read cycle time 15 ns t aa address to data valid 15 ns t oha data hold from address change 3 ns t ace ce low to data valid 15 ns t doe oe low to data valid 7 ns t lzoe oe low to low-z [7] 0ns t hzoe oe high to high-z [6, 7] 7ns t lzce ce low to low-z [7] 3ns t hzce ce high to high-z [6, 7] 7ns t pu ce low to power up 0 ns t pd ce high to power down 15 ns 1046b?3 1046b?4 90%v cc 10%v cc vcc gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) output r1 481 r1 481 r2 255 r2 255 167 equivalent to: venin equivalent 1.73v th rise time:1 v/ns fall time:1 v/ns notes 4. test conditions are based on signal transit ion times of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. this part has a voltage regulator which steps down the voltage from 5v to 3.3v internally. t power is the time that the power needs to be supplied above v cc (typ) initially before a read or write operation can be initiated. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-stat e voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 4 of 9 write cycle [8, 9] t wc write cycle time 15 ns t sce ce low to write end 10 ns t aw address setup to write end 10 ns t ha address hold from write end 0 ns t sa address setup to write start 0 ns t pwe we pulse width 10 ns t sd data setup to write end 8 ns t hd data hold from write end 0 ns t lzwe we high to low-z [7] 3ns t hzwe we low to high-z [6, 7] 7ns switching characteristics (over the operating range) [4] (continued) 7c1046bn-15 parameter description min max unit data retention characteristics (over the operating range) parameter description conditions [10] min max unit v dr v cc for data retention 2.0 v i ccdr data retention current com?l v cc = v dr = 2.0v, ce > v cc ? 0.3v v in > v cc ? 0.3v or v in < 0.3v 200 a t cdr [3] chip deselect to data retention time 0 ns t r operation recovery time 200 s data retention waveform 1046b?5 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc notes 8. the internal memory write time is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data setup and hold timing must be referenced to the leading edge of the signal that termina tes the write. 9. the minimum write cycle time for write cycle 3 (we controlled, oe low) is the sum of t hzwe and t sd . 10. no input may exceed v cc + 0.5v. [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 5 of 9 switching waveforms read cycle 1 [11, 12] read cycle 2 (oe controlled) [12, 13] previous data valid data valid t rc t aa t oha 1046b?6 address data out 1046b?7 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzce t pd high oe ce i cc i sb impedance address data out v cc supply current notes 11. device is continuously selected. oe , ce = v il . 12. we is high for read cycle. 13. address valid before or similar to ce transition low. [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 6 of 9 write cycle 1 (ce controlled) [14, 15] write cycle 2 (we controlled, oe high during write) [14, 15] switching waveforms (continued) 1046b?8 t wc data valid t aw t sa t pwe t ha t hd t sd t sce t sce ce address we data io t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe data in valid ce address we data io oe note 16 1046b?9 notes 14. data io is high impedance if oe = v ih . 15. if ce goes high simultaneously with we going high, the output remains in a high impedance state. 16. during this period the ios are in the output state and input signals must not be applied. [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 7 of 9 write cycle 3 (we controlled, oe low) [15] switching waveforms (continued) 1046b?10 data valid t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data io note 16 ordering information speed (ns) ordering code package diagram package type operating range 15 CY7C1046BN-15VC 51-85033 32-pin (400-mil) molded soj commercial [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 8 of 9 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. package diagram figure 1. 32-pin (400-mi l) molded soj, 51-85033 all products and company names mentioned in this docum ent may be the trademarks of their respective holders. 51-85033-*b [+] feedback [+] feedback
cy7c1046bn document #: 001-11924 rev. ** page 9 of 9 document history page document title: cy7c1046bn 1m x 4 static ram document number: 001-11924 rev. ecn no. issue date orig. of change description of change ** 610496 see ecn nxr new data sheet [+] feedback [+] feedback
|
